Keynote 1 – Secure Heterogeneous Integration and Advanced Packaging:
New Attack Surfaces and Grand Challenges Ahead
Mark M. Tehranipoor - University of Florida (US)
Abstract: Heterogeneous integration and advanced packaging have seen resurgence over the past few years. The notion of building a system in package from chiplets is quite attractive, however it comes with challenges of ensuring quality, reliability and security. Providing assurance for each chiplet, establishing a secure chiplet supply chain, ensuring secure and trusted integration, verifying and validating policies, etc are few important challenges that will be discussed in this presentation.
Bio: Mark M. Tehranipoor is currently the Intel Charles E. Young Preeminence Endowed Chair Professor and the Sachio Semmoto Chair of the Department of Electrical and Computer Engineering (ECE) at the University of Florida. His current research projects include: hardware security and trust, supply chain security, IoT security, VLSI design, test and reliability. He has 50+ patents issued/pending, 19 books, and 500+ conference/journal publications. He is a recipient of 18 best paper awards and nominations, as well as the 2008 IEEE Computer Society (CS) Meritorious Service Award, the 2012 IEEE CS Outstanding Contribution, the 2009 NSF CAREER Award, and the 2014 AFOSR MURI award. He received the 2020 University of Florida Innovation of the year as well as teacher/scholar of the year awards. He co-founded the IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), IEEE International Conference on Physical Assurance and Inspection of Electronics (PAINE). He serves on the program committee of more than a dozen leading conferences and workshops. He has also served as Program and General Chair of a number of IEEE and ACM sponsored conferences and workshops (HOST, ITC, DFT, D3T, DBT, NATW, and more). He is currently serving as a founding EIC for Journal on Hardware and Systems Security (HaSS) and served as Associate Editor for TC, JETTA, JOLPE, TODAES, IEEE D&T, TVLSI. He is currently serving as a founding director for Florida Institute for Cybersecurity Research (FICS) and a number of other centers with focus on microelectronics security. Dr. Tehranipoor is the recipient of the Semiconductor Research Corporation (SRC) Aristotle Award, a Fellow of the IEEE, a Fellow of the ACM, a Fellow of the National Academy of Inventors (NAI), a Golden Core Member of IEEE CS, and Member of ACM SIGDA.
Keynote 2 – Long Live Computing Technology
Dr. Rajiv Joshi - IBM Research (US)
Abstract: The explosion of computers and the internet significantly improved the quality of human life. Communication across the globe made the earth as one family. Building blocks of this computing power are fabricated from crucial and key semiconductor technology. This talk covers such building blocks and showcases their impact. Volatile and non-volatile memories (NVM) have proved to be focal points for research over decades. Memories in general are the workhorse of the semiconductor industry. Applications of these spread across many domains such as Artificial Intelligence (AI), servers, high-performance computing, Systems on Chip (SOC), Internet of Things (IoT), quantum computing, etc., and thus are essential components of the computing world. As we march forward the scaling of memories poses a major challenge to achieve functionality, performance, area, power, and yield. To overcome scaling issues the talk will describe alternative techniques and circuits. It will bring out challenges and future directions for various memory applications.
Bio: Dr. Rajiv V. Joshi is an IEEE Fellow, winner of the prestigious IEEE Daniel Noble award, and a key technical lead/Research Scientist at T. J. Watson Research Center, IBM. He received his B. Tech IIT (Bombay, India), M.S (MIT), and Dr. Eng. Sc. (Columbia University). He has successfully led innovations in technology, memories (SRAM, DRAM, and others), and predictive analytic techniques for yield prediction for IBM Server Groups and their products. His statistical techniques are tailored for machine learning and AI which are licensed and commercialized. His memory innovations and work are used in both IBM P and Z servers. His technology innovations set IBM’s leadership across the globe. He received 3 Outstanding Technical Achievement (OTAs), 3 highest Corporate Patent Portfolio awards for contributions in interconnect technologies, holds 73 invention plateaus, has over 290 US patents covering front end and back end of the line processes, and structures, volatile and non-volatile memories, Compute in Memory structures, machine learning algorithms, and quantum computing and over 425 international patents. He has authored and co-authored over 235 refereed papers, delivered over 60 invited/keynote talks, and given several Seminars. He received the NY IP Law Association “Inventor of the Year” award in Feb 2020. He is a Mercator Fellow at the University of Siegen, Germany. He received an industrial pioneer award in 2014 from the IEEE Circuits and Systems Society. He received the Best Editor Award from the IEEE TVLSI journal. He was inducted into the New Jersey Inventor Hall of Fame in Aug 2014. He won the Mehboob Khan Award two times from Semiconductor Research Corporation. He won several best paper awards from ISSCC 1992, VMIC 1998, ICCAD 2009, and ISQED 2014. He is a member of the IBM Academy of Technology and a master inventor. He serves on the Board of Governors for IEEE CAS as an industrial liaison. He served on EC for DAC, ISLPED, CICC, ISCAS, AICAS, and APCCAS (2023) committees as well as the AE of TCAS I and TVLSI. He served as a Distinguished Lecturer for IEEE CAS, CEDA, and EDS society. He is an ISQED and World Technology Network fellow and a distinguished alumnus of IIT Bombay. He served on the executive advisory committee for the Center of 3D Ferroelectric and Microelectronics at Penn State. He serves as an IEEE CAS Ambassador to India.
Keynote 3 – AI at the edge: Hype or Hope?
Henk Corporaal - Technical University of Eindhoven (NL)
Abstract: Artificial neural networks (ANNs), especially deep ones, have gained immense popularity. While their potential applications appear boundless, a significant drawback is their heavy reliance on cloud-based servers. This dependence stems from the exponential expansion in the size and computational requirements of these networks. For instance, the latest large language models like ChatGPT-4 boast over a trillion parameters and demand astonishing computational resources, in the order of 10^25 FLOPS, for training. Achieving this training task in a reasonable timeframe (i.e., less than a month) requires the use of thousands of cloud-based servers. Even a single inference takes about 5.10^14 FLOPS, making real-time inferencing extremely costly. We believe that there are substantial advantages in bringing intelligence directly to smart sensor devices at the network edge, performing the computation locally, close to the sensing data. However, these devices typically have a sub-Watt or even sub-mWatt power budget, and lack huge memories and compute capabilities. Achieving smart Edge-AI with less reliance on large AI servers necessitates a significant improvement in energy efficiency. This leads to the question: is AI at the edge really feasible, or is it a mindless dream? In this keynote, we address the state of the art (SOTA) in Edge computing and its trends and developments. We discuss what is needed to really bring AI to the Edge, how to bridge this huge energy-efficiency gap. Improvements are needed at all levels of the design stack; perhaps even new neural computing paradigms. We conclude by offering a glimpse into the future, exploring potential breakthroughs on the horizon.
Bio: Henk Corporaal is Professor in Embedded System Architectures at the Eindhoven University of Technology (TU/e) in The Netherlands. He has gained an MSc in Theoretical Physics from the University of Groningen, and a PhD in Electrical Engineering, in the area of Computer Architecture, from Delft University of Technology. His research is on low-power multi-processor, heterogeneous processing architectures, their programmability, and the predictable design of soft- and hard real-time systems. This includes research and design of embedded system architectures, including CGRAs, SIMD, VLIW, and GPUs, on accelerators, the exploitation of all kinds of parallelism, fault-tolerance, approximate computing, architectures for machine and deep learning, optimizations and mapping of deep learning networks, and the (semi-)automated mapping of applications to these architectures. Corporaal has co-authored over 500 journal and conference papers. Furthermore, he invented a new class of VLIW architectures, the Transport Triggered Architectures, which is used in several commercial products, and by many research groups. He initiated and leads the Dutch NWO perspectief program on Efficient Deep Learning (efficientdeeplearning.nl); in this program, many research institutes and over 30 companies participated. He also is the PI of the EU project CONVOLVE (convolve.eu) on seamless design of smart edge processors, with 19 partners. For further details see corporaal.org.